The integrated circuits are generally fabricated on silicon substrates. Substrates of “SOI” (Silicon On Insulator) type corresponding to substrates of silicon incorporating a layer of silica oxide SIO2 are commonly used in the microelectronics industry and notably for the fabrication of transistors, making it possible to reduce leakage currents.
FIG. 1 illustrates a conventional transistor scheme produced from a semiconductive substrate 1, and conventionally comprising a source 2a, a drain 2b and a gate 4, said gate being separated from a conductive channel 2, by an insulating material 3 also called gate insulator, and comprising elements 5a and 5b called insulating spacers, notably described in a patent application FR 2 872 626 of the Applicant.
Conventionally, the semiconductive material is locally doped so as to define the regions corresponding to the source and to the drain. This doping operation can notably be carried out by ion implantation, the nature of the ion species implanted, of electron donor or acceptor type, defining the nature of the transistor: transistor respectively called NMOS or PMOS.
In order to increase performance in terms of mobility and bearers of a transistor, it has already been shown that it was possible to act on the stresses exerted at the level of the layer of silicon (or of any other semiconductive material) of the SOI substrate, to increase the mobility of the bearers by virtue of the effect of a mechanical stress on a semiconductive material generating a very strong enhancement in the mobility of the bearers and therefore the electrical performance levels of the transistors.
The applicant has notably filed the patent application FR 2 872 626 relating to a method making it possible to stress or deform a pattern or a thin layer from an initial component comprising a prestress layer. This method comprises a step of etching the prestress layer at right angles to its surface. This prestress layer can be insulating or conductive but, for applications such as the control of the transport properties by deformation of the channel of an MOS transistor, it is preferably electrically insulating (for example made of Si3N4), in order to limit the leakage currents.
Other authors: J. G. Fiorenza “Detailed Simulation Study of a Reverse Embedded-SiGe Strained-Silicon MOSFET” IEEE Transactions on Electron Devices; Vol. 55, No. 2, p. 640; 2008, have proposed, on a similar principle, to transfer stress into the channel: a layer of SiGe with a germanium concentration of 35%, in compression induces a tension in the channel just above, simulations making it possible to optimize the process with certain physical and architectural parameters of the structure, as illustrated in FIG. 2.
The simulations of this publication show an optimization according to two criteria:                the maximization of the ratio of the thickness of the layer of SixGey (tSiGe) to the thickness of the higher layer of Si (tSi);        the aspect ratio AR=(tSiGe+tSi)/W with W being the length of the pattern produced, such that 0.3<AR<0.5.        
According to this structure, there is an advantage only from a stress point of view: the absence of buried oxide layer between the silicon and the prestress layer facilitates the transfer of stress.
Nevertheless, drawbacks remain:                the stress layer of SiGe has the same dimension as the gate with the spacer which is less than the dimension of the active area in the case of a transistor structure, whereas the reduction of this dimension is a factor reducing the stress transmitted.        the etching of the prestress layer takes place after the gate deposition step.        
Authors have also described, in the patent application US 2006/0163557, complex structures having a succession of several layers of SiGe.